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technical specification iq65033qma10 product # iq65033qma10 phone 1-888-567-9596 www.synqor.com doc.# 005-iq5033s rev. h 05/27/10 page 1 the iq65033qma10 iqor ? power interface module integrates all features required by the advancedtca base specification into a quarter-brick footprint. the iqor offers industry leading external hold-up capacitor volumetric density for a compact overall solution. at a 90v hold - up capacitor voltage (trimmable 50-95 v), only 564 f is required to achieve 8.70ms hold - up time at 200win. the -48 v output voltage is conditioned for smooth operation through severe input transient events. the iqor is designed thermally and electrically to drive high power wide-range-input dc/dc converters such as the 300 w synqor pq60120qea25. rohs compliant see last page. ? management power over-voltage protection ? management power over-current protection ? main output over-current protection ? thermal shutdown protects the unit from abnormal environmental conditions ? input fuse/feed loss alarm protection features ? 2250v, 30 m? vrtn_a/b to logic_gnd and shelf_gnd isolation ? ul/cul 60950-1 recognized (us & canada), basic insulation rating ? tuv certified to en60950-1 ? meets 72/23/eec and 93/68/eec directives which facilitates ce marking in users end product ? board and plastic components meet ul94v-0 flammability requirements safety features iq65033qma10 module 36-75v @ 10 a 3.3 v & 5.0 v quarter-brick atca input/output mgmt power power interface module ? input oring for a & b power feeds (mosfet-based for low power dissipation) ? hot swap control with seamless ride-through of input voltage transient ? emi filter meets cispr 22 class b when used as directed (see applications section) ? external hold-up capacitor trimmable from 50-95 v ? automatic discharge of external hold-up capacitor ? isolated management power of 3.3 v at 3.6 a and 5.0 v at 150 ma ? dual input side enable ? i 2 c interface data reporting (optional) operational features ? industry standard quarter-brick size: 1.45" x 2.3" (36.8x58.4 mm) ? overall height of 0.54" (13.7 mm), permits better airflow and smaller card pitch ? total weight: 1.2 oz (34 g) ? flanged pins designed to permit surface mount soldering (avoid wave solder) using fpip technique ? external hold-up capacitor footprint much smaller than other solutions currently available on the market mechanical features
input: outputs: current: package: 36-75 v 5.0 v/ 3.3 v 10 a quarter-brick product # iq65033qma10 phone 1-888-567-9596 www.synqor.com doc.# 005-iq5033s rev. h 05/27/10 page 2 y notes 1) all pins are 0.040" (1.02 mm) diameter with 0.080" (2.03 mm) diameter standoff shoulders. 2) other pin extension lengths available. recommended pin length is 0.03" (0.76 mm) greater than the pcb thickness. 3) all pins: material - copper alloy finish - matte tin over nickel plate 4) undimensioned components are shown for visual reference only. 5) all dimensions in inches (mm) tolerances: x.xx + 0.02" (x.x + 0.5 mm) x.xxx + 0.010" (x.xx + 0.25 mm) 6) weight: 1.2 oz (34 g) typical 7) workmanship: meets or exceeds ipc-a-610c class ii 8) the flanged pins are designed to permit surface mount soldering (allowing to avoid the wave soldering process) through the use of the flanged pin-in-paste technique. * pins 10, 11, and 12 are only available on the full feature version. see the ordering page for more information. ** single resistor connected externally to logic_gnd selects the three least significant bits of i 2 c address 0101xxx. pin no. name function 1 -48v_a negative a feed (externally fused) 2 -48v_b negative b feed (externally fused) 3 vrtn_a positive a feed (externally fused) 4 vrtn_b positive b feed (externally fused) 5 enable_a enable a input (externally fused) (short pin tied to vrtn_a on backplane) 6 enable_b enable b input (externally fused) (short pin tied to vrtn_b on backplane) 7 shelf_gnd shelf ground 8 5.0v 5.0v (relative to logic_gnd) 9 3.3v 3.3v (relative to logic_gnd) 10 i2c_adr i 2 c address input * (connect external resistor to logic_gnd) ** 11 i2c_dat i 2 c data (relative to logic_gnd) * 12 i2c_clk i 2 c clock (relative to logic_gnd) * 13 logic_gnd logic ground 14 alarm isolated a/b feed loss or open fuse alarm (relative to logic_gnd) 15 -48v_out negative output to payload power converter 16 hu_trim hold-up voltage trim (connect external resistor to -48v_out) 17 vrtn_out positive output to payload power converter 18 hu_cap positive connection to hold-up capacitor (negative connection to -48v_out) pin designations mechanical diagram top view side view 0.100 (2.54) 0.150 (3.81) overall height 0.54 (13.7) bottom side clearance 0.064 0.028 (1.63 0.71) 0.150 (3.81) 2.30 (58.42) 2.00 (50.8) 1.45 (36.83) 1.45 (36.83) 0.200 (5.08) 0.200 (5.08) 0.200 (5.08) 0.200 (5.08) 0.200 (5.08) 0.225 (5.72) 0.150 (3.81) 0.150 (3.81) 0.150 (3.81) 0.950 (24.13) 1 2 3 4 8 9 10 11 12 13 14 6 7 5 15 16 17 18 lowest component load board flanged pin see note 8 see note 2
input: outputs: current: package: 36-75 v 5.0 v/ 3.3 v 10 a quarter-brick product # iq65033qma10 phone 1-888-567-9596 www.synqor.com doc.# 005-iq5033s rev. h 05/27/10 page 3 y parameter \ min. typ. max. units notes & conditions absolute maximum ratings input voltage continuous -75 v limited by internal tvs zener diode transient -100 v 1ms transient, square wave reverse polarity +75 v no damage, low current, output diode clamped isolation voltage (vrtn_a/b to logic_gnd) 2250 v (vrtn_a/b to shelf_gnd) 2250 v operating temperature -40 100 c subject to thermal derating; see figures 1 & 3 storage temperature -55 125 c hold-up capacitor voltage (relative to -48v_out) 100 v -48v dual feed input characteristics input voltage range -34 -48 -75 v subject to the threshold protocol used operating current 10 a 25oc 950 lfm, vin = -48v; see figure 1 disabled input current below turn-off threshold 8 10 ma enabled no-load input current 21 30 ma vin = -48v internal input filter capacitance (not hot-swapped) 18 22 f should be precharged by resistors to early_a/b pins recommended early_a/b resistors 100 w surge rated 2010 case size (koa sg73 series or equiv.) recommended input fuses 15 a 3.3v isolated management power startup delay time from enable_a/b to 3.3/5.0vout at 36vin 0.43 0.50 s at 48vin 0.31 s at 75vin 0.15 0.20 s turn-on rise time 1 5 20 ms 0% to 90%; see figure 10 input under-voltage lockout turn-on voltage threshold (atca) -33.5 -34.5 -36.0 v at mangement power converter input; see figure a turn-off voltage threshold (atca) -32.0 -34.0 -35.5 v turn-on voltage threshold (neds) -33.5 -34.5 -36.0 v turn-off voltage threshold (neds) -32.0 -34.0 -35.5 v turn-on voltage threshold (etsi) -25.5 -26.5 -28.0 v ; overriden by enable turn-off voltage threshold (etsi) -24.0 -26.0 -27.5 v ; overriden by enable total output voltage range 3.170 3.350 3.430 v including line, load, sample, life, and temp output voltage ripple and noise see figure 12 peak-to-peak 40 75 mv full load, 10f ceramic, 500mhz bandwidth rms 16 30 mv operating output current range 0 3.6 a subject to thermal derating; see figures 1 & 3 output dc current-limit inception 3.9 5.4 6.9 a current limit shutdown voltage 1.5 v initiates hiccup mode hiccup mode restart time 130 ms vin = -48v back-drive current 10 ma negative current drawn from output source maximum output capacitance 1000 f switching frequency 200 220 240 khz management power converter over-voltage protection setpoint 4.10 4.33 4.55 v 5.0v power (derived from 3.3v converter) total output voltage range 4.80 1 5.00 5.20 v including line, load, sample, life, and temp operating output current range 0 150 ma short circuit current 400 ma independent thermal protection back-drive current 1 ma negative current drawn from output source maximum output capacitance 1000 f temperature limits for power derating curves semiconductor junction temperature 125 c package rated to 150c board temperature 125 c ul rated max operating temp 130c transformer temperature 125 c see figure 3 for derating curve iq65033qma10 electrical characteristics specifcations subject to change without notice. specifcations in bold are guaranteed by design over the temperature range -40o to 125oc.
input: outputs: current: package: 36-75 v 5.0 v/ 3.3 v 10 a quarter-brick product # iq65033qma10 phone 1-888-567-9596 www.synqor.com doc.# 005-iq5033s rev. h 05/27/10 page 4 y parameter \ min. typ. max. units notes & conditions dual enable input characteristics enable_a/b threshold v atca 26.0 28.5 31.0 v at input feed voltage -48v_a/b; see figure a neds (on\off) 40.0\36.0 42.5\39.0 45.0\42.0 v etsi 32.0 34.0 36.0 v current drain per enable pin (vin = -75v) 0.36 ma -48v output efficiency no load on 3.3v/5.0v outputs, vin = -48v 300w output power 97.7 98.2 200w output power 98.0 98.5 equivalent resistance from input feed 120 200 m w recommended external output filter capacitance 80 100 270 f see note 2 hot-swap startup ramp dv/dt 150 200 250 v/s output voltage delay 250 650 ms no load; depends on external cap.; see figure 5 input current limit (turns off hot-swap momentarily) 15 17.5 20 a hold-up still active input dv/dt limit (turns off hot-swap momentarily) 40 v/ms short circuit duration to initiate hiccup mode 2 ms restart time in hiccup mode 1.8 2.0 2.2 s input oring oring mosfet turn on current 0.4 1.0 2.4 a oring mosfet turn off current 0.1 0.4 1.1 a oring mosfet current hysteresis 0.3 0.6 1.3 a turn on time 600 s turn off time 0.25 s hold-up capacitor interface hold-up capacitor trim range 50 90 95 v can be set either above or below input voltage hold-up capacitor charge accuracy 87.2 90.0 92.8 v 2.49k ? external trim resistance, 1% 100ppm/oc external hold-up voltage trim resistor power dissipation 160 w hold-up capacitor charge current 40 ma switching frequency 405 450 495 khz hold-up power converter -48v_out threshold see note 3 to arm hold-up (atca/neds options) -36.9 -38.9 -40.9 v at vrtn_out w.r.t. -48v_out; see figure a to initiate hold-up (atca/neds) -36.4 -38.5 -40.4 v to arm hold-up connect (etsi) -32.4 -34.5 -36.4 v to initiate hold-up connect (etsi) -32.4 -34.5 -36.4 v dv/dt on hold-up connect 80 v/ms duration of hold-up connect 0.1 s see note 4 delay before hold-up connect is (re)armed 2 s 48v output still enabled hold-up capacitor discharge resistance 1.55 1.65 1.75 k ? maximum hold-up capacitance 3300 f yields 55ms (200 w at 90 v cap charge) isolated alarm output (alarm = hiz) 5 input a/b feed voltage alarm threshold 36.4 38.4 40.4 v at input feed voltage -48v_a/b; see figure a open circuit voltage 40 v on-state voltage 0.2 0.4 v at 50ma on-state transistor collector current 50 ma off-state transistor collector current 1 a iq65033qma10 electrical characteristics (continued) specifcations subject to change without notice. specifcations in bold are guaranteed by design over the temperature range -40o to 125oc. note 1: if the 5.0 v load current exceeds 100 ma, up to 200 mv of additional voltage drop is possible on the 5.0 v output. note 2: maximum dc load at startup is 50 ma . full load can be applied 700 ms after enable or 400 ms after the management power is up and running. note 3: hold-up operation with vin < 43 v not required by atca specification. note 4: 48 v output does not recover after hold-up event unless input is above arm hold-up threshold. note 5: does not inhibit 48 v output and is non-latching.
input: outputs: current: package: 36-75 v 5.0 v/ 3.3 v 10 a quarter-brick product # iq65033qma10 phone 1-888-567-9596 www.synqor.com doc.# 005-iq5033s rev. h 05/27/10 page 5 y iq65033qma10 electrical characteristics (continued) specifcations subject to change without notice. specifcations in bold are guaranteed by design over the temperature range -40o to 125oc. parameter p min. typ. max. units notes & conditions i 2 c data reporting interface maximum clock rate 100 400 khz clock stretching happens at the maximum rate measurement error feed voltage a/b + 3 % holdup voltage + 3 % -48v_out current + 3 % temperature + 3 c over-temperature protection shutdown point 135 c does not shut down management power restart hysteresis 10 c automatic restart reliability characteristics calculated mtbf (telcordia) 3.6 10 6 hrs. tr-nwt-000332; 80% load,300lfm, 40 o c t a calculated mtbf (mil-217) 3.27 10 6 hrs. mil-hdbk-217f; 80% load, 300lfm, 40 o c t a field demonstrated mtbf 10 6 hrs. see website for details standards compliance parameter p notes standards compliance ul/cul 60950-1 file # e194341, basic insulation & pollution degree 2 en60950-1 certified by tuv 72/23/eec 93/68/eec needle flame test (iec 695-2-2) test on entire assembly; board & plastic components ul94v-0 compliant iec 61000-4-2 esd test, 8kv - np, 15kv air - np (normal performance) gr-1089-core section 7 - electrical safety, section 9 - bonding/grounding telcordia (bellcore) gr-513 ? an external input fuse must always be used to meet these safety requirements. contact synqor for official safety certificates on new releases or download from the synqor website. qualification testing parameter p # units test conditions qualification testing life test 32 95% rated v in and load, units at derating point, 1000 hours vibration 5 10-55hz sweep, 0.060 total excursion,1 min./sweep, 120 sweeps for 3 axes mechanical shock 5 100g minimum, 2 drops in x and y axis, 1 drop in z axis temperature cycling 10 -40c to 100c, unit temp. ramp 15c/min., 500 cycles power/thermal cycling 5 t operating = min to max, v in = min to max, full load, 100 cycles design marginality 5 t min -10c to t max +10c, 5c steps, v in = min to max, 0-105% load humidity 5 85c, 85% rh, 1000 hours, 2 minutes on and 6 hours off solderability 15 pins mil-std-883, method 2003 ? extensive characterization testing of all synqor products and manufacturing processes is performed to ensure that we supply robust, reliable product. contact the factory for official product family qualification documents.
input: outputs: current: package: 36-75 v 5.0 v/ 3.3 v 10 a quarter-brick product # iq65033qma10 phone 1-888-567-9596 www.synqor.com doc.# 005-iq5033s rev. h 05/27/10 page 6 y i # t c u d 65 65 q #5 c5 u yyyefn yen 400 lfm (2.0 m/s) 300 lfm (1.5 m/s) 200 lfm (1.0 m/s) 100 lfm (0.5 m/s) figure 1: -48v output (maximum power) derating curves vs. ambient air tem - perature for airflow rates of 100 lfm through 400 lfm with air flowing across the converter from pin 7 to pin 1 (48 vin, 3.3v mgmt power output @ 1.5 a). figure 2: thermal plot of converter at 6.2a load current from -48v out - put (298w) with 55 c air flowing at the rate of 200 lfm. air is flowing across the converter from pin 7 to pin 1 (48 vin, 3.3v output @ 1.5 a). 1.0 1.5 2.0 2.5 3.0 3.5 4.0 10 25 40 55 70 85 ambient air temperature (c) iout (a) 400 lfm (2.0 m/s) 300 lfm (1.5 m/s) 200 lfm (1.0 m/s) 100 lfm (0.5 m/s) figure 3: 3.3v output (maximum power) derating curves vs. ambient air tem - perature for airflow rates of 100 lfm through 400 lfm with air flowing across the converter from pin 7 to pin 1 (48 vin, main output power output @ 4 a). figure 4: thermal plot of converter at 2.9a load current from 3.3v out - put (9.6w) with 55 c air flowing at the rate of 200 lfm. air is flowing across the converter from pin 7 to pin 1 (48 vin, -48v output @ 4 a). figure 5: 48v hot-swap turn-on transient (100uf electrolytic filter capacitor cf). top trace: vrtn_out w.r.t. -48v_out (20v/div), bottom trace: input feed current (2a/div). figure 6: 8.70ms zero volt transient (564uf electrolytic hold-up capaci - tor ch, 100uf electrolytic filter capacitor cf). ch 1: input feed a/b voltage (20v/div). ch 2: vrtn_out w.r.t. -48v_out (20v/div). ch 3: hu_cap w.r.t. -48v_out (20v/div). ch 4: 3.3v_out (200mv/div).
input: outputs: current: package: 36-75 v 5.0 v/ 3.3 v 10 a quarter-brick product # iq65033qma10 phone 1-888-567-9596 www.synqor.com doc.# 005-iq5033s rev. h 05/27/10 page 7 y figure 7: instantaneous input transient from 48v feed a to 60v feed b. ch 1: input feed a voltage (20v/div). ch 2: input feed b voltage (20v/ div). ch 3: vrtn_out w.r.t. -48v_out (20v/div). ch 4: 3.3v_out (200mv/div). figure 8: inductive switching event on feed a from 48v to 0v to tvs zener clamping voltage. no load on -48v output. ch1: input feed a voltage (20v/div). ch3: vrtn_out w.r.t. -48v_out (20v/div). ch 4: 3.3v_out (50mv/div). 0 1 2 3 4 5 6 7 8 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 load current (a) power dissipation (w) 36 vin 48 vin 75 vin figure 9: power dissipation vs. 3.3v load current with hot-swap switch enabled. figure 10: management power turn on transient at 50% load (4ms/div). load capacitance: 10uf ceramic capacitor. ch 2: 3.3vout (1v/div). ch 3: 5.0vout (1v/div). figure 12: 3.3vout ripple at nominal input voltage at rated load current (20mv/div). load capacitance: 10uf ceramic capacitor. bandwidth: 500mhz. figure 11: 3.3vout response to a step-change in load current (50%- 75%-50% of iout(max): di/dt = 1a/us). load capacitance: 10uf ceramic capacitor. top trace: 3.3vout (500mv/div). bottom trace: iout (1a/ div).
input: outputs: current: package: 36-75 v 5.0 v/ 3.3 v 10 a quarter-brick product # iq65033qma10 phone 1-888-567-9596 www.synqor.com doc.# 005-iq5033s rev. h 05/27/10 page 8 y feature descriptions figure a: internal block diagram a em i f ilt er hot swap contro l logic cu rr ent- contro ll ed hold- up charging converter hold-up connec t con tr ol circu it s management power converter fet control fet control fet control fet control dis- charge enable logic a b c d b c d te mp sense -48_b ena bl e_a en ab le_b -48_a vrtn_a vrtn_b shelf_gnd l og ic_gnd alarm 3.3v 5.0 v -48v_ ou t vrtn_out hu_t ri m hu_cap 5 6 3 4 1 2 7 41 31 8 9 15 16 17 18 isola ti on barrier e f dv/dt sense f e e f 10 11 12 i 2 c data i 2 c a dd . i 2 c cl ock m on it ori ng circuits input oring mosfets: oring of dual -48v feeds is provided by four mosfets, which are individually controlled so as to oper - ate as an ideal diode (see figure a). if there is an input feed short of any kind, a control circuit will detect reverse current and turn off the mosfet in 250ns (typ.), to avoid disturbing the other feed voltage. at zero current, the mosfet is guaranteed to be off. in the case of a fuse failure, this triggers the alarm output, due to an apparent input feed loss. current hysteresis prevents limit cycling around the transition point between body diode and mosfet conduction. alarm output: the alarm pin gives an external indication of a fault condition. it is an isolated and buffered open-collector output, which is normally pulled low. in the presence of an input feed loss (which can be caused by a fuse failure), the alarm out - put will be tri-stated. external input fuse failure detection: at zero current, the input oring mosfets are guaranteed to be off. in the case of a fuse failure, an on-board bleed resistor pulls the input feed voltage down. this triggers the alarm output due to an apparent input feed loss. there are two main down-sides to this approach. first, there is no way to distinguish between a feed loss and a fuse fail - ure. second, an enable fuse loss is not detected, since the enables are diode ord. the full featured version of the iqor offers additional data report - ing that makes full fuse detection possible. among other data, each feed voltage and each enable voltage is reported through the i 2 c port. these voltages can be compared with the voltages reported by the shelf manager to determine whether any board fuse is blown.
input: outputs: current: package: 36-75 v 5.0 v/ 3.3 v 10 a quarter-brick product # iq65033qma10 phone 1-888-567-9596 www.synqor.com doc.# 005-iq5033s rev. h 05/27/10 page 9 y input enable: the enable_a/b signals connect to vrtn_a/b on the backplane via the shortest pins in the zone 1 connector. they are the last pins to mate during board insertion, and the first to disconnect during board extraction. the enable_a and enable_b signals are diode-ored together which lets either sig - nal enable the module. whenever both enable pins are open, the hot-swap switch is opened. this prevents -48v output power from being drawn though the early pre-charge resistors. the enable signals also control the management power. on board insertion, the management power remains off until at least one of enable_a/b is connected. on board extraction, the management power is disabled at the end of the 100ms hold-up period, and remains off until enable_a/b is reconnected. this prevents the ipmi controller from reading an invalid hardware address when a board is partially inserted. management power flows through the early pre-charge resistors for a maximum of 100ms, which provides a margin similar to the pre-charge event in terms of resistor safe-operating-area. early precharge resistors: the early_a/b signals connect to the longest pins in the zone 1 power connector, and therefore first to mate during board insertion. external resistors connected between these signals and vrtn_a/b allow the relatively small emi filter capacitance to be pre-charged before the main power pins make contact. a 100 w surge rated 2010 case size resistor is recommended (koa sg73 series or equivalent). hot swap - thermal shutdown: to protect the unit from damage in an abnormal thermal environment, the hot-swap switch will be disabled when the thermal sensor temperature rises above the turn-off threshold. the switch will be automatically enabled again when the temperature goes below the turn-on threshold. the management power remains on during an over-temperature condition. the full featured version of the iqor reports the actual temperature through the i 2 c port. hot swap - over-current protection: if the -48v output current rises above the current limit threshold, the hot-swap switch will be disabled, and will immediately enter another soft-start sequence. if an output short is detected, the hot-swap switch will be disabled and will enter a hiccup mode of operation with automatic restart. the full featured version of the iqor reports actual output current through the i 2 c port. hot swap - transient suppression: input transient events can occur if there is a short on an adjacent board or backplane. the short builds up a large current in the wiring inductance, and when a fuse blows, the voltage behind the fuse spikes very quickly. this can cause a loss of redundancy since many other boards could be exposed to this spike. the iqor unit conditions the -48v output, providing for seam - less ride-through of input voltage transients. if the positive dv/ dt of the input voltage is too high, the hot-swap switch will be disabled and will immediately enter another soft-start sequence. this limits the dv/dt seen on the -48v output, which prevents the 12v payload power converter from having such a large glitch on its output that it shuts down. the -48v output hold-up function remains active throughout, in case the hot-swap switch is forced off for too long. passive transient suppression: each input feed has a dedi - cated internal bidirectional tvs zener diode, rated for a minimum clamp voltage of 77.8v at 1ma. a tvs diode short due to electri - cal overstress will not disable the iqor module: a fuse will open, and the module can continue to run from the other feed. external hold-up capacitor charge: a current controlled dc-dc converter charges the external hold-up capacitor to a volt - age of 50v-95v, set by an external resistor. the charge voltage can range either above or below the input feed voltage. constant current charging takes place whenever the hot-swap switch is enabled. hold-up capacitor connect: when the hot-swap switch is enabled, 2 seconds are allocated to charge the hold-up capaci - tor. after this time, a comparator is armed, which connects the hold-up capacitor to the -48v output should the output ever drop below the given connect threshold. a current limit circuit protects against damage during a short circuit condition. a dv/dt limit cir - cuit regulates the hold-up connect switch turn-on speed. when the comparator is tripped, the hold-up connect switch remains closed for 100ms, is off for 2 seconds to allow the hold-up capacitor to recharge, and then is automatically rearmed (if the output voltage is above the given arm threshold). hold-up capacitor discharge: whenever the hot-swap switch is disabled, an internal resistor bank is connected across the hold-up capacitor. this is intended to reduce the voltage on the hold-up capacitor below 60v within 1 second. management power: an isolated management power converter delivers both 3.3v and a low power 5.0v relative to logic_gnd. over-current protection operates in constant current with a hiccup mode if the output voltage drops too far. output over-voltage circuitry is included with a redundant refer - ence and optocoupler.
input: outputs: current: package: 36-75 v 5.0 v/ 3.3 v 10 a quarter-brick product # iq65033qma10 phone 1-888-567-9596 www.synqor.com doc.# 005-iq5033s rev. h 05/27/10 page 10 y hot swap C shutdown timing: in the event of a sudden loss of input voltage (see figure b), a hold-up event will be triggered. when the output voltage (plus a diode drop for the hot-swap body diode) decays to the management power under-voltage turn-off threshold, the main -48v output and the 3.3v/5.0v outputs will shut down simultaneously. in the event of a gradual loss of input voltage (see figure c), the main -48v output will shut down 100ms after the beginning of the hold-up event. the -48v output will enter a hiccup mode of operation for input voltages below the hold-up arm threshold. management power will continue to run until the input voltage (plus 0v to 1.2v for the oring mosfets) decays to the manage - ment power under-voltage turn-off threshold. figure b: sudden loss of input power i npu t vo lt a g e a l a r m p a y l o a d ou t pu t 4 8 v m anag e m en t po w e r 4 8 v 0 4 8 v 3 . 3 v 0 0 h o l d u p e v e n t 3 4 . 6 v t yp . 3 9 v t yp . ( d e p e nd s o n ver si on ) ( p u l l - u p vo lt a g e l o st ) h o l d u p ti m e , t h 0 figure c: gradual loss of input power m anag e m en t po w e r ou t pu t ( 3 . 3v ) - l o g i c _ g n d - 4 8 v ou t pu t v o l t ag e v r t n o u t - ( - 4 8 v _ o u t ) h i ghe r o f a / b i npu t f e e d vo l t a ge s v r t n a / b - ( - 4 8 v _ a / b ) 4 8 v 0 4 8 v 3 . 3 v 0 0 a l a r m - ( l o g i c _ g n d ) 3 8 . 5 v t yp i cal ( d e pe n d s o n ver si on ) ( p u l l u p vo lt a g e l o s t ) 3 8 . 4 v t yp . 1 0 0 m s h o l d u p e v e n t 3 4 . 0 ( d e pe n d s o n ver si on ) 3 8 . 9 v t yp . o u t p u t i s of f a ft e r d e l a y i f i n p u t vo l t a g e d oe s n t r e cove r a b o ve 3 8 . 9 v t y p . m a n a ge m e n t po w e r t u r n e d o f f a t h i gh e r o f e n ab l e t h r e s ho l d o r m p u v l o .
input: outputs: current: package: 36-75 v 5.0 v/ 3.3 v 10 a quarter-brick product # iq65033qma10 phone 1-888-567-9596 www.synqor.com doc.# 005-iq5033s rev. h 05/27/10 page 11 y external hold-up capacitor selection c h is the hold-up capacitance (electrolytic capacitors typically have a 20% tolerance): c h = 2t h p h equation a v2 h C v2 u typically a strong function of v h (see figure d). the atca specification requirement is 8.70ms (see figure e). where: v h = hold-up capacitor charge voltage. v u = minimum operating voltage on the 48v output; the greater of the under-voltage lockout threshold of the payload power converter, and the under-voltage lockout threshold of the management power converter. t h = time from when the highest input feed voltage drops below v f , to the time when the highest input feed voltage rises above v u . v f = voltage at which the hold-up capacitor is engaged. p h = power drawn from the hold-up capacitor, the sum of the input power of the payload power converter, and the input power of the 3.3v mgmt power converter (see figure 9): p h = p out 12v + p in 3.3v equation b 12v p out12v = output power delivered by the payload converter. 12v = efficiency of the 12v payload converter. p in.3.3v = 3.3v input management converter power. external hold-up capacitor voltage rating operating electrolytic capacitors near their voltage rating does not significantly affect their reliability, as it does with tantalum or ceramic type capacitors. the operating life of electrolytic capacitors is primarily determined by the capacitor internal temperature. the capacitor lifetime roughly doubles for every 10oc reduction in internal temperature. synqor recommends running 100v rated electrolytic capacitors at 90v, which dramatically increases hold-up time for a given capacitor volume (see figure d). a built-in circuit automatically discharges the hold - up capacitor when the input voltage is removed. 0 5 1 0 1 5 2 0 3 0 0 h o l d - u p t i m e ( m s ) 4 0 0 5 0 0 6 0 0 7 0 0 8 0 0 9 0 0 1 0 0 0 h o l d - u p c a p a c i t a n c e ( f ) 9 0 v 8 0 v 7 0 v p h = 2 0 0 w c f = 1 0 0 f v i = - 4 3 v figure d: hold-up time (ms) vs. hold-up capacitance ( f) at hold-up charge voltages of 70v, 80v, and 90v (see equation a). the advancedtca hold-up time requirement is at most 8.70ms (solid horizontal line). the capacitor tolerance is not factored into this result. error bars indicate the worst case range of hold-up time for a given hold-up capacitance. 3 6 . 0 v 4 3 . 0 v 4 1 . 0 v 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 0 1 2 3 4 5 6 7 8 9 1 0 ti m e ( m s ) inp u t f e e d v ol ta g e (v) 8 . 7 0 m s figure e: the picmg 3.0 r2.0 advancedtca base specification requires continuous operation through a zero-volt transient, lasting 5ms (section 4.1.2.2). however, this is not a square wave: the voltage starts at a minimum amplitude of -43v, falls at 50v/ms, remains at 0v for 5ms, and then rises at 12.5v/ms. at the worst case values of the hold-up connect threshold and the management power under-voltage lockout threshold, the required hold-up time is 8.70ms.
input: outputs: current: package: 36-75 v 5.0 v/ 3.3 v 10 a quarter-brick product # iq65033qma10 phone 1-888-567-9596 www.synqor.com doc.# 005-iq5033s rev. h 05/27/10 page 12 y external hold-up trim resistor selection r trim is the external hold-up trim resistance for a given desired nomi - nal hold-up capacitor charge voltage ( v hu ) (see figure f): r trim = ( 500,000 C 10,000 ) ? equation c v hu C 50.0 1 0 0 0 1 0 00 0 1 0 00 0 0 5 0 6 0 7 0 8 0 9 0 1 0 0 h o l d - u p c h a r g e v o l t a g e ( v ) e x t e r n a l h o l d - up t r i m r es i s t a n ce ( ) ? figure f: plot of equation c, used to choose the external trim resistor value based on the desired hold-up capacitor charge voltage. error bars indicate the worst case range of charge voltage for a given exter - nal trim resistor value (assumes 1%, 100ppm for external trim resistor tolerance). worst case calculation over temp range -40oc to 125oc. figure g: application diagram s hi el d pl ane * s y nq or i q or a t ca p ow er input m odul e e ar ly a e ar l y b - 48v a - 48v b rt n 48v a rt n 48 v b e nabl e b e nabl e a s hel f g nd 10 0 o h ms hu _ ca p v r t n _ o u t hu _ t r i m - 48 v _ o u t r t r i m c h p ay l oad p ow er conv er ter pq 6 01 2 0 q e a 2 5 a l a r m 5 . 0 v i 2 c c l o c k i 2 c d a t a i 2 c a d d r es s 3 . 3 v l og i c _ gn d 3 . 3 ko h ms 3. 3v t o ip m b l ue le d bi as (f ro m i pm ) 12v 1 0 0 o h ms - 4 8 v _ a - 4 8 v _ b v r t n _ a v r t n _ b e n a b l e _ a e n a b l e _ b s h e l f _ g n d i 2 c i n t e r f ac e o n f u l l - f e a t u r e d v e r s i o n on l y 1 0 o h ms 1 0n f 1 0n f * s hi el d pl ane s houl d ex t end under pa yl oad power c onv er t er hol dup c apac i t or 1 0 0 f 1 0 0 v a l ar m
input: outputs: current: package: 36-75 v 5.0 v/ 3.3 v 10 a quarter-brick product # iq65033qma10 phone 1-888-567-9596 www.synqor.com doc.# 005-iq5033s rev. h 05/27/10 page 13 y full feature application notes i 2 c data reporting interface: available on the full feature version of the module, the iqor i 2 c serial interface monitors 5 analog parameters and 6 status bits. the actual analog parameter values are calculated by multiplying by the specified scaling factors (see table 1). the status bits are interpreted in table 2. the initial value of all registers is zero. data in the registers begins updating 300 ms after management power startup, and continues updating at approximately 100 ms intervals during steady-state operation. all registers are updated simulatneously. i 2 c protocol: reading from any internal register of the iqor monitor requires that an internal (pseudo) register, data_pointer, be initialized prior to reading (see figure h). data_pointer is write-only. it is written from the second byte of any i 2 c write message (the first byte is the 7 bit i 2 c address and the rw bit). subsequent data bytes in a write message (3 rd byte and beyond) only increment data_pointer. any read message will return the value of the internal register referenced by data_pointer and increments data_pointer by one. for instance, if the master acknowledges (ak), the next internal register referenced by data_pointer will be returned and data_pointer will be incremented by one. this process is repeated until the master does not acknowledge (nack) and issues a stop bit. data_pointer is an 8bit value. it is initialized to 00h at reset, and after reaching ffh, it will not overflow. writing to registers not defined in table 1 has no effect. reading from these undefined registers will return 00h. in both cases data_pointer is incremented. example from the point of view of the i 2 c master: 1) start transmission. 2) send 56h (addresses unit for writing, given address 56h was selected as shown in table 4). 3) send 22h (loads 22h into data_pointer). 4) stop transmission. 5) start next transmission. 6) send 57h (addresses unit for reading). 7) unit will respond with the value of -48v_a (register 22h as shown in table 1). 8) ack (data_pointer is automatically incremented to 23h). 9) unit will respond with the value of -48v_b (register 23h). 10) nack. 11) stop transmission. bit name description value translation 0 enable_a enable a signal state 0 en_a is disabled 1 en_a is enabled 1 enable_b enable b signal state 0 en_b is disabled 1 en_b is enabled 2 alarm alarm signal state 0 primary side alarm is not set 1 primary side alarm is set 3 n/a reserved 4 holdup holdup switch state 0 holdup cap is not connected to -48v out 1 holdup cap is connected to -48v out 5 hotswap hotswap switch state 0 hotswap switch is off 1 hotswap switch is on 6 vout_ low -48v output u nder-voltage alarm 0 output voltage is below threshold 1 output voltage is above threshold 7 n/a reserved data_pointer value parameter description scaling factor 1 eh status bits digital signals (see table 2) n/a 1fh hu_cap voltage between hu_ cap and -48v_out 0.39 8 v/bit 21h -48v_current -48v output current 0.09 4 a/bit 22h -48v_a voltage between vrtn_a and -48v_a 0.3 25 v/bit 23h -48v_b voltage between vrtn_b and -48v_b 0.3 25 v/bit 28h temperature average unit temperature (1.961 oc/bit) C 50 oc table 1: internal register memory map. table 2: the status byte represents 6 different digital signals and their digital state. note: 1) bit0 ? lsb, bit7 ? msb. figure h: typical i 2 c read transmission. note: s = start, w = write, r = read, ak = acknowledged, nack = not acknowl - edged, p = stop. clear boxes originate in the i 2 c master and shaded boxes originate in the i 2 c slave.
input: outputs: current: package: 36-75 v 5.0 v/ 3.3 v 10 a quarter-brick product # iq65033qma10 phone 1-888-567-9596 www.synqor.com doc.# 005-iq5033s rev. h 05/27/10 page 14 y i 2 c address structure: 7 bit i 2 c address + rw bit four bits are fixed (0101), three bits (xyz) are variable, and the least-significant bit is the read/write bit. i 2 c address selection: the three bits (xyz) of the i 2 c address are set with a single external resistor from the i2c_adr (pin 10) to logic_gnd (pin 13). the 8 possible addresses are shown in table 4 with the respective resistance values. external programming res i stances for i 2 c a ddress selection i 2 c address for write (r w = 0) xyz from table 3 r ( w ) 5eh 111 open 5ch 110 100000 5ah 101 40200 58h 100 20000 56h 011 10000 54h 010 4020 52h 001 2000 50h 000 short table 4: i 2 c address selection. table 3: i 2 c address structure. 8 bit i 2 c address 0 1 0 1 x y z * r w
input: outputs: current: package: 36-75 v 5.0 v/ 3.3 v 10 a quarter-brick product # iq65033qma10 phone 1-888-567-9596 www.synqor.com doc.# 005-iq5033s rev. h 05/27/10 page 15 y part numbering system the part numbering system for synqors dc-dc converters follows the format shown in the example below. the first 12 characters comprise the base part number and the last 3 characters indicate available options. the -g suffix indicates 6/6 rohs compliance. application notes a variety of application notes and technical white papers can be downloaded in pdf format from our website. rohs compliance: the eu led rohs (restriction of hazardous substances) directive bans the use of lead, cadmium, hexavalent chromium, mercury, polybrominated biphenyls (pbb), and polybrominated diphenyl ether (pbde) in electrical and electronic equipment. this synqor product is 6/6 rohs compliant. for more information please refer to synqors rohs addendum available at our rohs compliance / lead free initiative web page or e-mail us at rohs@synqor.com . ordering information the tables below show the valid model numbers and ordering options for converters in this product family. when ordering synqor converters, please ensure that you use the complete 15 character part number consisting of the 12 character base part number and the additional 3 characters for options. add -g to the model number for 6/6 rohs compliance. the following options must be included in place of the x y z spaces in the model numbers listed above. not all combinations make valid part numbers, please contact synqor for availability. see the product summary web page for more options. warranty synqor offers a t hree ( 3 ) year limited warranty. complete warranty informa - tion is listed on our website or is available upon request from synqor. information furnished by synqor is believed to be accurate and reliable. however, no responsibility is assumed by synqor for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of synqor. product family package size performance level thermal design output current 6/6 rohs options (see ordering information) input voltage output voltage contact synqor for further information: phone : 978-849-0600 toll free : 888-567-9596 fax : 978-849-0602 e-mail : power@synqor.com web : www.synqor.com address : 155 swanson road boxborough, ma 01719 usa i q 6 5 0 3 3 q m a 1 0 s n s - g yoy x y z threshold protocols pin style feature set s - standard (atca) n - neds e - etsi k - 0.110" n - 0.145" r - 0.180" y - 0.250" s - standard f - full feature model numer input voltage mmt power 36-75v input/ utput current i65033ma10 xyz 36 - 75 v 5.0 v & 3.3 v 10 a patents synqor holds the following u.s. patents, one or more of which apply to each product listed in this document. additional patent applications may be pending or filed in the future. 5,999,417 6,222,742 6,545,890 6,577,109 6,594,159 6,731,520 6,894,468 6,896,526 6,927,987 7,050,309 7,072,190 7,085,146 7,119,524 7,269,034 7,272,021 7,272,023 7,558,083 7,564,702

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